The present invention relates to a polishing pad for use in chemical mechanical planarization applications. More particularly, the present invention relates to a pad used in the chemical mechanical planarization or polishing of semiconductor wafers.
Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips. A common technique for forming the circuitry on a semiconductor is photolithography. Part of the photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive toward smaller, more highly integrated circuit designs. Semiconductor wafers are also commonly constructed in layers, where a portion of a circuit is created on a first level and conductive vias are made to connect up to the next level of the circuit. After each layer of the circuit is etched on the wafer, an oxide layer is put down allowing the vias to pass through but covering the rest of the previous circuit level. Each layer of the circuit can create or add unevenness to the wafer that is preferably smoothed out before generating the next circuit layer.
Chemical mechanical planarization (CMP) techniques are used to planarize the raw wafer and each layer of material added thereafter. Available CMP systems, commonly called wafer polishers, often use a rotating wafer holder that brings the wafer into contact with a polishing pad moving in the plane of the wafer surface to be planarized. A polishing fluid, such as a chemical polishing agent or slurry containing microabrasives, is applied to the polishing pad to polish the wafer. The wafer holder then presses the wafer against the rotating polishing pad and is rotated to polish and planarize the wafer.
The type of polishing pad used on the wafer polisher can greatly affect the removal rate profile across a semiconductor wafer. Ideally, a semiconductor wafer processed in a wafer polisher will see a constant removal rate across the entire wafer surface. Many polishing pads have been designed with one particular pattern of channels or voids to attempt to achieve a desired removal rate. These existing polishing pads often have a signature removal rate pattern that, for example, may remove material from the edge of a semiconductor wafer faster than the inner portion of the wafer. Accordingly, there is a need for a polishing pad that will enhance uniformity across the surface of a semiconductor wafer.
According to a first aspect of the present invention, a polishing member is provided having a linear belt movable in a linear path. At least two serially linked polishing pad sections are attached to the belt. The polishing pad sections include a first polishing pad section having a first groove pattern formed in a side of the first polishing pad section. The first groove pattern is preferably made up of a plurality of grooves. A second polishing pad section has a non-grooved side opposite the linear belt.
According to a second aspect of the present invention, a polishing pad for chemical mechanical planarization of semiconductor wafers includes a plurality of serially linked polishing pad sections forming a linear belt. The plurality of serially linked polishing pad sections includes first and second polishing pad sections having respective first and second groove patterns. In one embodiment, each of the groove patterns is preferably oriented parallel to the linear path of the pad. In another embodiment, the pad sections may have non-parallel grooves.
According to another aspect of the present invention, a method of producing a linear chemical mechanical planarization polishing pad having a plurality of polishing pad sections includes the step of empirically measuring the material removal rate profile on a semiconductor wafer for each of a plurality of groove patterns used in chemical mechanical planarization polishing pads, wherein each of the plurality of groove patterns is a unique groove pattern. The measured material removal rate profile for each of the plurality of groove patterns is then compared and a determination is made as to an appropriate combination of the different groove patterns to achieve improved removal rate uniformity across a semiconductor wafer. After determining the necessary combination, a polishing pad comprised of at least two serially linked polishing pad sections is fabricated, where at least two of the polishing pad sections include a different one of the selected groove patterns.